integrated device technology, inc. commercial temperature ranges august 1996 1996 integrated device technology, inc. 10.1 dsc-3255/3 octal bus switch idt74fst3244 idt74fst32244 preliminary features: bus switches provide zero delay paths extended commercial range of ?0 c to +85 c low switch on-resistance: fst3xxx ?5 w fst32xxx ?28 w ttl-compatible input and output levels esd > 2000v per mil-std-883, method 3015; > 200v using machine model (c = 200pf, r = 0) available in qsop, tssop, soic and pdip pin-compatible with fct244/fct244t 1 their own while providing a low resistance path for an external driver. these devices connect input and output ports through an n-channel fet. when the gate-to-source junction of this fet is adequately forward-biased the device conducts or the resistance between input and output ports is small. without adequate bias on the gate-to-source junction of the fet, the fet is turned off, therefore with no v cc applied, the device has hot insertion capability. the low on-resistance and simplicity of the connection between input and output ports reduces the delay in this path to close to zero. the fst32244 integrates terminating resistors in the de- vice, thus eliminating the need for external 25 w series resis- tors. the fst3244 and fst32244 are octal ttl-compatible bus switches. the oe pins provide output enable control for all 8 bits. functional block diagram pin configuration pin description oe a da 0 da 1 da 2 da 3 oa 0 oa 1 oa 2 oa 3 oe b db 0 db 1 db 2 db 3 ob 0 ob 1 ob 2 ob 3 pin names description oe a , oe b output enable inputs (active low) da 0-3 , oa 0-3 a port bits db 0-3 , ob 0-3 b port bits 3255 drw 01 3255 drw 02 3255 tbl 03 the idt logo is a registered trademark of integrated device technology, inc. the fst3244/32244 belong to idt's family of bus switches. bus switch devices perform the function of connecting or isolating two ports without providing any inherent current sink or source capability. thus they generate little or no noise of description: 5 6 7 8 9 10 1 2 3 4 18 17 16 15 14 13 12 11 gnd da 0 ob 0 da 1 ob 1 da 2 ob 2 da 3 ob 3 oa 0 db 0 oa 1 db 1 oa 2 db 2 oa 3 db 3 vcc oe a p20-1 so20-2 so20-8 so20-9 19 20 oe b dip/soic/ qsop/tssop top view
10.1 2 idt74fst3244, idt74fst32244 octal bus switch commercial temperature ranges function table absolute maximum ratings (1) dc electrical characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = ?0 c to +85 c, v cc = 5.0v 5% capacitance (1) note: 1. h = high voltage level l = low voltage level x = don't care oe oe a oe oe b oa ob description h h hi-z hi-z disconnect l h da hi-z connect h l hi-z db connect l l da db connect 3255 tbl 03 symbol parameter test conditions (1) min. typ. (2) max. unit v ih input high voltage guaranteed logic high for control inputs 2.0 v v il input low voltage guaranteed logic low for control inputs 0.8 v i i h input high current v cc = max. v i = v cc 1 m a i i l input low voltage v i = gnd 1 i ozh high impedance output current v cc = max. v o = v cc 1 m a i ozl (3-state output pins) v o = gnd 1 i os short circuit current v cc = max., v o = gnd (3) 300 ma v ik clamp diode voltage v cc = min., i in = C18ma C0.7 C1.2 v r on switch on resistance (4) v cc = min. v in = 0.0v 3xxx 5 7 w i on = 30ma 32xxx 17 28 40 v cc = min. v in = 2.4v 3xxx 10 15 w i on = 15ma 32xxx 20 35 48 i off input/output power off leakage v cc = 0v, v in or v o 4.5v 1 m a i cc quiescent power supply current v cc = max., v i = gnd or v cc 0.1 3 m a notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. not more than one output should be tested at one time. duration of the test should not exceed one second. 4. measured by voltage drop between ports at indicated current through the switch. 3255 lnk 05 symbol description max. unit v term (2) terminal voltage with respect to gnd C0.5 to +7.0 v t stg storage temperature C65 to +150 c i out maximum continuous channel current 128 ma notes: 1. stresses greater than those listed under absolute maximum rat- ings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating condiitions for extended periods may affect reliability. 2. v cc , control and switch terminals. 3255 tbl 02 symbol parameter conditions (2) typ. unit c in control input capacitance 4 pf c i/o switch input/output capacitance switch off pf 3255 tbl 04 notes: 1. capacitance is characterized but not tested 2. t a = 25 c, f = 1mhz, vi n = 0v, v out = 0v
10.1 3 idt74fst3244, idt74fst32244 octal bus switch commercial temperature ranges power supply characteristics switching characteristics over operating range following conditions apply unless otherwise specified: commercial: t a = C40 c to +85 c, v cc = 5.0v 5% symbol parameter test conditions (1) min. typ. (2) max. unit d i cc quiescent power supply current ttl inputs high v cc = max. v in = 3.4v (3) 0.5 1.5 ma i ccd dynamic power supply current (4) v cc = max. outputs open v in = v cc v in = gnd 3040 m a/ mhz/ enable pin toggling 50% duty cycle switch i c total power supply current (6) v cc = max. outputs open enable pin toggling v in = v cc v in = gnd 1.2 1.6 ma (4 switches toggling) fi = 10mhz 50% duty cycle v in = 3.4 v in = gnd 1.5 2.4 notes: 1. for conditions shown as max. or min., use appropriate value specified under electrical characteristics for the applicable device type. 2. typical values are at v cc = 5.0v, +25 c ambient. 3. per ttl driven input (v in = 3.4v). all other inputs at v cc or gnd. 4. this parameter is not directly testable, but is derived for use in total power supply calculations. 5. values for these conditions are examples of the i cc formula. these limits are guaranteed but not tested. 6. i c = i quiescent + i inputs + i dynamic i c = i cc + d i cc d h n t + i ccd (f i n) i cc = quiescent current d i cc = power supply current for a ttl high input (v in = 3.4v) d h = duty cycle for ttl inputs high n t = number of ttl inputs at d h i ccd = dynamic current caused by an input transition pair (hlh or lhl) f i = input frequency n = number of switches toggling at f i all currents are in milliamps and all frequencies are in megahertz. 3255 tbl 06 3244 32244 symbol description condition (1) min. (2) typ. max. unit t plh t phl data propagation delay da, db to oa, ob oa, ob to da, db (3,4) c l = 50pf r l = 500 w 0.25 1.25 ns t pzh t pzl switch turn on delay oe a to da, oa, oe b to db, ob 1.5 6.5 7.5 ns t phz t plz switch turn off delay oe a to da, oa, oe b to db, ob (3) 1.5 5.5 5.5 ns |q ci | charge injection (5,6) 1.5 pc notes: 1. see test circuit and waveforms. 2. minimum limits guaranteed but not tested. 3. this parameter is guaranteed by design but not tested. 4. the bus switch contributes no propagation delay other than the rc delay of the on resistance of the switch and the load capacitance. the time constant for the switch alone is of the order of 0.25 ns for 50 pf load. since this time is constant and much smaller than the rise/fall times of typical driving signals, it adds very little propagation delay to the system. propagation delay of the bus switch when used in a system is determined by the driving circuit on the driving side of the switch and its interaction with the load on the driven side. 5. measured at switch turn off, load = 50 pf in parallel with 10 m w scope probe, v in = 0.0 volts. 6. characterized parameter. not 100% tested. 3255 tbl 07
10.1 4 idt74fst3244, idt74fst32244 octal bus switch commercial temperature ranges test circuits and waveforms test circuits for all outputs switch position propagation delay enable and disable times pulse width set-up, hold and release times test switch disable low enable low closed all other tests open open drain definitions: c l = load capacitance: includes jig and probe capacitance. r t = termination resistance: should be equal to z out of the pulse generator. notes: 1. diagram shown for input control enable-low and input control disable- high 2. pulse generator for all pulses: rate 1.0mhz; t f 2.5ns; t r 2.5ns pulse generator r t d.u.t. v cc v in c l v out 50pf 500 w 500 w 7.0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v 3v 1.5v 0v data input timing input asynchronous control preset clear etc. synchronous control t su t h t rem t su t h high-low-high pulse low-high-low pulse t w 1.5v 1.5v same phase input transition 3v 1.5v 0v 1.5v v oh t plh output opposite phase input transition 3v 1.5v 0v t plh t phl t phl v ol control input 3v 1.5v 0v 3.5v 0v output normally low output normally high switch closed switch open v ol 0.3v 0.3v t plz t pzl t pzh t phz 3.5v 0v 1.5v 1.5v enable disable v oh preset clear clock enable etc. 3255 lnk 08 3255 lnk 03 3255 lnk 04 3255 lnk 05 3255 lnk 06 3255 lnk 07
10.1 5 idt74fst3244, idt74fst32244 octal bus switch commercial temperature ranges ordering information 3255 drw 08 idt xx temp. range xx device type x package 74 C40 c to +85 c p so q pg 3244 32244 plastic dip (p20-1) small outline ic (so20-2) quarter-size small outline package (so20-8) thin shrink small outline package (so20-9) octal bus switch fst
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